With the continual improvement of semiconductor chip fabrication techniques, the number of devices which can be packed onto a semiconductor chip has increased greatly, while the size of the individual devices have decreased markedly. Today several million devices can be fabricated in a single chip--consider, for example, the mega-bit memory chips which are commonly used today in personal computers and in other applications. In such high-density chips, elements must be insulated properly in order to obtain good performance. The main purpose of element insulation techniques is to provide good insulation between the elements of the devices using smaller insulation area, to provide more space for more devices and their elements.
An effective method of achieving good insulation is the so-called Silicon-On-Insulator (SOI) technique. Structurally it comprises a single-crystal silicon layer deposited on an insulator, usually thinner than 1 .mu.m. An insulation trench can be formed until it reaches the insulator, thereby forming insulated silicon islands on the insulator, where devices can be formed with excellent insulation from devices formed in neighboring islands.
Among SOI techniques, a common technique is Separation by IMplanted OXygen (called "SIMOX"). The SIMOX process steps are shown in FIGS. 1A to 1C and are discussed below.
At first a silicon substrate 10 is provided. Oxygen ions are implanted into the substrate 10 which is thereafter annealed to convert the region implanted by oxygen ions into a buried oxide layer 11 formed in the substrate 10 beneath its surface. Thus, the substrate 10 is divided into two portions, a surface portion 15 and a bottom portion 16 by the buried oxide 11, as is shown in FIG. 1A.
Referring now to FIG. 1B, trenches 12 are formed by etching predetermined regions of the surface 15. Then an isolating material is deposited filling the trenches 12 and forming lateral isolators 13 which divide the surface 15 into a plurality of active regions or islands 14, as is shown in FIG. 1C. The active regions 14 are completely isolated in such a structure.
Although the isolation effect works very well using the SIMOX technique, it suffers from a relatively high parasitic capacitance between the bottom portion 16 and the active regions 14 so that the operating speed of devices formed in the islands 14 is limited. Since the buried oxide layer 11 is formed by implantation, its maximum thickness is about 0.5 .mu.m, therefore the parasitic capacitance can not be reduced. Additionally, many defects and residual stresses appear at the interface between the active regions 14 and the buried oxide layer 11, which reduce the reliability of IC's manufactured using this technology.